DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 988

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
18.4.6
This module can be operated with the clock synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
(1)
Figure 18.13 shows the clock synchronous serial transfer format.
The transfer data is output from the fall to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
Rev. 3.00 May 17, 2007 Page 930 of 1582
REJ09B0181-0300
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
ICDRR
ICDRS
Data Transfer Format
RDRF
SCL
SDA
SDA
SCL
User
Clock Synchronous Serial Format
2
C Bus Interface 2 (I
Figure 18.13 Clock Synchronous Serial Transfer Format
Figure 18.12 Slave Receive Mode Operation Timing (2)
SCL
SDA
A
9
Bit 7
1
2
C2)
Bit 0
Bit 6
Data 1
2
Bit 1 Bit 2 Bit 3 Bit 4
Bit 5
3
Bit 4
4
Bit 3
5
[3] Set ACKBT
Bit 2
6
Bit 5 Bit 6
Bit 1
7
[3] Read ICDRR [4] Read ICDRR
Bit 0
Bit 7
8
A
9
Data 1
Data 2