DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 416

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Tables 9.29 to 9.34 list the minimum number of idle cycles to be inserted for the normal space
interface and the SDRAM interface. The CSnBCR Idle Setting column in the tables describes the
number of idle cycles to be set for IWW, IWRWD, IWRWS, IWRRD, and IWRRS.
Rev. 3.00 May 17, 2007 Page 358 of 1582
REJ09B0181-0300
A. Insert one idle cycle to access the interface other than the SDRAM interface after the write
B. Insert one idle cycle to access the SDRAM interface after the normal space interface with
C. Insert one idle cycle to access the SDRAM interface after the MPX-I/O interface is
D. Insert two idle cycles to access the MPX-I/O interface from the external bus that is in the
E. Insert one idle cycle to access the MPX-I/O interface after a read cycle is performed in the
F. Insert two idle cycles to access the MPX-I/O interface after a write cycle is performed in
access cycle is performed in the SDRAM interface.
the external wait invalidated or the byte-selection SRAM interface with the BAS bit = 0
specified is accessed.
accessed.
idle status.
normal space interface, byte-selection SRAM interface with the BAS bit = 0, and the
SDRAM interface.
the SDRAM interface.