DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 956

IC SUPERH MCU FLASH 112LQFP

DF70844AD80FPV

Manufacturer Part Number
DF70844AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70844AD80FPV

Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
16KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70844AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF70844AD80FPV
Quantity:
5 000
Section 17 Synchronous Serial Communication Unit (SSU)
17.5
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive
data register full, and a transmit data register empty can activate the DTC for data transfer.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 17.8 lists the
interrupt sources.
When an interrupt condition shown in table 17.8 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DTC data transfer.
Table 17.8 SSU Interrupt Sources
Rev. 3.00 May 17, 2007 Page 898 of 1582
REJ09B0181-0300
Abbreviation
SSERI
SSRXI
SSTXI
SSU Interrupt Sources and DTC
Interrupt Source
Overrun error
Conflict error
Receive data register full
Transmit data register empty SSTXI
Transmit end
Symbol Interrupt Condition
SSOEI
SSCEI
SSRXI
SSTEI
(RIE = 1) • (ORER = 1) 
(CEIE = 1) • (CE = 1)
(RIE = 1) • (RDRF = 1) Yes
(TIE = 1) • (TDRE = 1)
(TEIE = 1) • (TEND = 1) 
DTC Activation
Yes

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