DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 973

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
5
4
3
Bit Name
RDRF
NACKF
STOP
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Receive Data Register Full
[Setting condition]
•
[Clearing conditions]
•
•
•
No Acknowledge Detection Flag*
[Setting condition]
•
[Clearing condition]
•
Stop Condition Detection Flag
[Setting conditions]
•
•
[Clearing condition]
•
When a receive data is transferred from ICDRS to
ICDRR
When 0 is written to RDRF after reading RDRF = 1
When ICDRR is read
DTC is activated by IIRXI interrupt and the DISEL
bit in MRB of DTC is 0.
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is 1
When 0 is written to NACKF after reading NACKF
= 1
In master mode, when a stop condition is detected
after frame transfer
In slave mode, when a stop condition is detected
after the slave address in the first byte that came
following the detection of a start condition have
matched the address set in SAR.
When 0 is written to STOP after reading STOP = 1
Rev. 3.00 May 17, 2007 Page 915 of 1582
Section 18 I
2
C Bus Interface 2 (I
REJ09B0181-0300
2
C2)