DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 522

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 May 17, 2007 Page 464 of 1582
REJ09B0181-0300
Bit
6
5
4
3
Bit Name
TTGE2
TCIEU
TCIEV
TGIED
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
A/D Converter Start Request Enable 2
Enables or disables generation of A/D converter start
requests by TCNT_4 underflow (trough) in
complementary PWM mode.
In channels 0 to 3, bit 6 is reserved. It is always read as
0 and the write value should always be 0.
0: A/D converter start request generation by TCNT_4
1: A/D converter start request generation by TCNT_4
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0 and the write value should always be 0.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 3 is reserved. It is always read
as 0 and the write value should always be 0.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
underflow (trough) disabled
underflow (trough) enabled