DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 447

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.3.4
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Initial value:
Initial value:
Bit
31 to 24
23
22
21, 20
19
18
Note:
R/W:
R/W:
Bit:
Bit:
*
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
R/W
DMA Channel Control Registers_0 to _3 (CHCR_0 to CHCR_3)
31
15
R
0
0
Bit Name
—
DO
TL
—
—
—
-
DM[1:0]
R/W
30
14
R
0
0
-
R/W
29
13
R
0
0
-
SM[1:0]
Initial
Value
All 0
0
0
All 0
0
0
R/W
28
12
R
0
0
-
R/W
27
11
R
0
0
-
R/W
R
R/W
R/W
R
R
R
R/W
26
10
R
0
0
-
RS[3:0]
Descriptions
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
Transfer End Level
This bit specifies the TEND signal output is high active
or low active.
0: Low-active output of TEND
1: High-active output of TEND
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
Undefined value is set when the DMAC is activated.
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
25
R
0
9
0
-
R/W
24
R
0
8
0
-
Section 10 Direct Memory Access Controller (DMAC)
R/W
R/W
DO
23
DL
0
7
0
R/W
R/W
Rev. 3.00 May 17, 2007 Page 389 of 1582
22
DS
TL
0
6
0
R/W
21
TB
R
0
5
0
-
R/W
20
R
0
4
0
-
TS[1:0]
R/W
19
R
0
3
0
-
REJ09B0181-0300
R/W R/(W)* R/W
18
R
IE
0
2
0
-
R/W
17
AM
TE
0
1
0
R/W
16
DE
AL
0
0
0