DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 960

IC SUPERH MCU FLASH 112LQFP

DF70844AD80FPV

Manufacturer Part Number
DF70844AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70844AD80FPV

Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
16KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70844AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF70844AD80FPV
Quantity:
5 000
Section 18 I
Clock synchronous serial format:
• Four interrupt sources
Rev. 3.00 May 17, 2007 Page 902 of 1582
REJ09B0181-0300
[Legend]
ICCR1 :
ICCR2 :
ICMR :
ICSR :
ICIER :
ICDRT :
ICDRR :
ICDRS :
SAR :
NF2CYC :
SCL
SDA
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
The data transfer controller (DTC) can be activated by a transmit-data-empty request or
receive-data-full request to transfer data.
I
I
I
I
I
I
I
I
Slave address register
NF2CYC register
2
2
2
2
2
2
2
2
2
C Bus Interface 2 (I
C bus control register 1
C bus control register 2
C bus mode register
C bus status register
C bus interrupt enable register
C bus transmit data register
C bus receive data register
C bus shift register
Noise canceler
Noise canceler
Figure 18.1 Block Diagram of I
Output
control
Output
control
2
C2)
decision circuit
decision circuit
Arbitration
Bus state
Transmission/
control circuit
reception
NF2CYC
ICDRT
ICDRS
ICDRR
2
C Bus Interface 2
ICIER
Transfer clock
comparator
generation
Address
ICCR1
ICCR2
circuit
ICMR
ICSR
SAR
generator
Interrupt
Interrupt
request

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