DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 83

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.2.1
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are
used for data processing and address calculation. R0 is also used as an index register. With a
number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack
pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the
status register (SR) and program counter (PC) values.
2.2.2
There are three 32-bit control registers, designated status register (SR), global base register
(GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base
address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers.
VBR is used as a base address of the exception handling (including interrupts) vector table.
• Status register (SR)
Initial value:
Initial value:
Bit
31 to 10
9
8
7 to 4
3, 2
R/W:
R/W:
Bit:
Bit:
General Registers (Rn)
Control Registers
31
15
R
R
0
0
-
-
Bit
name

M
Q
I[3:0]

30
14
R
R
0
0
-
-
Default
All 0
Undefined
Undefined
1111
All 0
29
13
R
R
0
0
-
-
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
Read/
Write
R
R/W
R/W
R/W
R
26
10
R
R
0
0
-
-
R/W
25
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Interrupt Mask
Reserved
These bits are always read as 0. The write value
should always be 0.
R
0
9
M
-
-
R/W
24
R
Q
0
8
-
-
R/W
23
R
0
7
1
-
R/W
22
R
0
6
1
Rev. 3.00 May 17, 2007 Page 25 of 1582
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I[3:0]
R/W
21
R
0
5
1
-
R/W
20
R
0
4
1
-
19
R
R
0
3
0
-
-
REJ09B0181-0300
18
R
R
0
2
0
-
-
Section 2 CPU
R/W
17
R
0
1
S
-
-
R/W
16
R
0
0
T
-
-