DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 72

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 1 Overview
Rev. 3.00 May 17, 2007 Page 14 of 1582
REJ09B0181-0300
Classification
System control
Interrupts
Address bus
Data bus
Symbol
RES
MRES
WDTOVF
BREQ
BACK
NMI
IRQ7 to IRQ0 I
IRQOUT
A29 to A0
D31 to D0
I/O
I
I
O
I
O
I
O
O
I/O
Name
Power-on reset
Manual reset
Watchdog timer
overflow
Bus-mastership
request
Bus-mastership
request
acknowledge
Non-maskable
interrupt
Interrupt requests
7 to 0
Interrupt request
output
Address bus
Data bus
Function
When low, this LSI enters the power-
on reset state.
When low, this LSI enters the
manual reset state.
Output signal for the watchdog timer
overflow. If this pin need to be pulled
down, use the resistor larger than
1 MΩ to pull this pin down.
Low when an external device
requests the release of the bus
mastership.
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Non-maskable interrupt request pin.
Fix to high or low level when not in
use.
Maskable interrupt request pin.
Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release
state.
Outputs addresses.
A24 to A0 are available in the
SH7083.
A25 to A0 are available in the
SH7084/SH7085.
32-bit bidirectional bus.
D15 to D0 are available in the
SH7083/SH7084.