DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 650

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
2. Basic Operation Example of A/D Converter Start Request Delaying Function
3. Buffer Transfer
4. A/D Converter Start Request Delaying Function Linked with Interrupt Skipping
Rev. 3.00 May 17, 2007 Page 592 of 1582
REJ09B0181-0300
Figure 11.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation
A/D converter start request
Figure 11.80 shows a basic example of A/D converter request signal (TRG4AN) operation
when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter
start request signal is output during TCNT_4 down-counting.
The data in the timer A/D converter start request cycle set registers (TADCORA_4 and
TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer
registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits
in the timer A/D converter start request control register (TADCR_4).
A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR).
Figure 11.81 shows an example of A/D converter start request signal (TRG4AN) operation
when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D
converter start requests are linked with interrupt skipping.
Figure 11.82 shows another example of A/D converter start request signal (TRG4AN)
operation when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter
start requests are linked with interrupt skipping.
TADCOBRA_4
TADCORA_4
Transfer from cycle buffer
register to cycle register
(TRG4AN)
Transfer from cycle buffer
register to cycle register
TCNT_4
Transfer from cycle buffer
register to cycle register
(Complementary PWM mode)