DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 531

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

• TSR_5
Bit
7 to 3
2
Bit Name
—
CMFU5
Note:
1.
Initial value:
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Value
All 0
0
R/W:
Bit:
R/W
R
R/(W)*
R
7
0
-
R
6
0
-
1
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Compare Match/Input Capture Flag U5
Status flag that indicates the occurrence of TGRU_5
input capture or compare match.
[Setting conditions]
•
•
•
[Clearing conditions]
•
•
R
5
0
-
When TCNTU_5 = TGRU_5 and TGRU_5 is
functioning as output compare register
When TCNTU_5 value is transferred to TGRU_5 by
input capture signal and TGRU_5 is functioning as
input capture register
When TCNTU_5 value is transferred to TGRU_5 and
TGRU_5 is functioning as a register for measuring the
pulse width of the external input signal. The transfer
timing is specified by the IOC bits in timer I/O control
register U_5 (TIORU_5).*
When DTC is activated by a TGIU_5 interrupt and the
DISEL bit of MRB in DTC is 0
When 0 is written to CMFU5 after reading CMFU5 = 1
R
4
0
-
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R
3
0
-
R/(W)*
CMFU5 CMFV5 CMFW5
Rev. 3.00 May 17, 2007 Page 473 of 1582
0
2
1
R/(W)*
1
0
1
2
R/(W)*
0
0
1
REJ09B0181-0300