DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 817

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1
Set the PFC for the external pins to be
Set the RIE, TIE, TEIE, and MPIE bits
Set CKE1 and CKE0 bits in SCSCR
Set TE and RE bits of SCSCR to 1
simultaneously.
TE, and RE bits in SCSCR to 0*
Clear RIE, TIE, TEIE, MPIE,
Set data transfer format in
< Initialization completed>
used (SCK, TXD, RXD)
(TE and RE bits are 0)
1-bit interval elapsed?
Set value in SCBRR
SCSMR, SCSDCR
Figure 15.3 Sample Flowchart for SCI Initialization
Start initialization
in SCSCR
Yes
Wait
No
[1]
[2]
[3]
[4]
[5]
Section 15 Serial Communication Interface (SCI)
[1] Set the clock selection in SCSCR.
[2] Set the data transfer format in SCSMR
[3] Write a value corresponding to the bit
[4] Set PFC of the external pin used. Set
[5] Set the TE bit or RE bit in SCSCR to 1.*
and SCSDCR.
rate to SCBRR. Not necessary if an
external clock is used.
RXD input during receiving and TXD
output during transmitting. Set SCK
input/output according to contents set by
CKE1 and CKE0. When CKE1 and
CKE0 are 0 in asynchronous mode,
setting the SCK pin is unnecessary.
Outputting clocks from the SCK pin
starts at synchronous clock output
setting.
Also make settings of the RIE, TIE,
TEIE, and MPIE bits. At this time, the
TXD, RXD, and SCK pins are ready to
be used. The TXD pin is in a mark state
during transmitting, and RXD pin is in an
idle state for waiting the start bit during
receiving.
Rev. 3.00 May 17, 2007 Page 759 of 1582
REJ09B0181-0300