DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 257

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.5.6
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB
set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB,
MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the
chain transfer operation.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source
flag for the activation source and DTCER are not affected.
In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB
to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed.
Chain Transfer
SAR
(When Transfer Destination is Specified as Block Area)
Figure 8.8 Memory Map in Block Transfer Mode
Transfer source data area
Nth block
1st block
:
:
:
Transfer
Transfer destination data area
(specified as block area)
Block area
Rev. 3.00 May 17, 2007 Page 199 of 1582
Section 8 Data Transfer Controller (DTC)
DAR
REJ09B0181-0300