DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 446

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
10.3.2
DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer.
During a DMA transfer, these registers indicate the next destination address. When the data is
transferred from an external device with the DACK in single address mode, the DAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the destination address
value. The initial value is undefined.
Initial value:
Initial value:
10.3.3
DMATCR are 32-bit readable/writable registers that specify the DMA transfer count. The number
of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and
16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers
indicate the remaining transfer count.
The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To
transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The initial value is undefined.
Initial value:
Initial value:
Rev. 3.00 May 17, 2007 Page 388 of 1582
REJ09B0181-0300
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/W
R/W
R/W
DMA Destination Address Registers_0 to _3 (DAR_0 to DAR_3)
DMA Transfer Count Registers_0 to _3 (DMATCR_0 to DMATCR_3)
31
15
31
15
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
30
14
30
14
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
29
13
29
13
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
28
12
28
12
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
27
11
27
11
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
26
10
26
10
R
0
0
0
0
-
-
-
-
R/W
R/W
R/W
25
25
R
0
9
0
0
9
0
-
-
-
-
R/W
R/W
R/W
24
24
R
0
8
0
0
8
0
-
-
-
-
R/W
R/W
R/W
R/W
23
23
0
7
0
0
7
0
-
-
-
-
R/W
R/W
R/W
R/W
22
22
0
6
0
0
6
0
-
-
-
-
R/W
R/W
R/W
R/W
21
21
0
5
0
0
5
0
-
-
-
-
R/W
R/W
R/W
R/W
20
20
0
4
0
0
4
0
-
-
-
-
R/W
R/W
R/W
R/W
19
19
0
3
0
0
3
0
-
-
-
-
R/W
R/W
R/W
R/W
18
18
0
2
0
0
2
0
-
-
-
-
R/W
R/W
R/W
R/W
17
17
0
1
0
0
1
0
-
-
-
-
R/W
R/W
R/W
R/W
16
16
0
0
0
0
0
0
-
-
-
-