DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 328

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
(7)
• CS0WCR
Initial value:
Initial value:
Rev. 3.00 May 17, 2007 Page 270 of 1582
REJ09B0181-0300
Bit
6
5 to 0
Bit
31 to 18
17, 16
R/W:
R/W:
Burst ROM (Clock Synchronous)
Bit:
Bit:
31
15
R
R
Bit Name
WM

0
0
Bit Name

BW[1:0]
-
-
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial
Value
0
All 0
Initial
Value
All 0
00
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R/W
R/W
R
R/W
R
R/W
R/W
26
10
R
0
1
-
Description
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted in the
second or subsequent access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
R/W
25
R
0
9
0
-
W[3:0]
R/W
24
R
0
8
1
-
R/W
23
R
0
7
0
-
R/W
WM
22
R
0
6
0
-
21
R
R
0
5
0
-
-
20
R
R
0
4
0
-
-
19
R
R
0
3
0
-
-
18
R
R
0
2
0
-
-
R/W
17
R
0
1
0
-
BW[1:0]
R/W
16
R
0
0
0
-