DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 915

IC SUPERH MCU FLASH 112LQFP

DF70844AD80FPV

Manufacturer Part Number
DF70844AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70844AD80FPV

Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
16KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70844AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF70844AD80FPV
Quantity:
5 000
16.7.6
The SCIF operation can be disabled or enabled using the standby control register. The initial
setting is for SCIF operation to be halted. Access to registers is enabled by clearing module
standby mode. For details, refer to section 26, Power-Down Modes.
16.7.7
When data is written to SCFTDR by activating the DTC through a TXIF interrupt, the TEND flag
value is undefined. In this case, do not use the TEND flag as a transmit end flag.
16.7.8
The FER flag and PER flag in the serial status register (SCFSR) are status flags that apply to next
entry to be read from the receive FIFO data register (SCFRDR). After the CPU or DTC reads the
receive FIFO data register, the flags of framing errors and parity errors will disappear.
To check the received data for the states of framing errors and parity errors, only read the receive
FIFO register after reading the serial status register.
Module Standby Mode Setting
Note on Using DTC
FER Flag and PER Flag of Serial Status Register (SCFSR)
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 May 17, 2007 Page 857 of 1582
REJ09B0181-0300

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