DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 734

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
12.2
The MTU2S has the following registers. For details on register addresses and register states during
each process, refer to section 27, List of Registers. To distinguish registers in each channel, an
underscore and the channel number are added as a suffix to the register name; TCR for channel 3
is expressed as TCR_3S.
Table 12.3 Register Configuration
Rev. 3.00 May 17, 2007 Page 676 of 1582
REJ09B0181-0300
Register Name
Timer control register_3S
Timer control register_4S
Timer mode register_3S
Timer mode register_4S
Timer I/O control register H_3S TIORH_3S R/W
Timer I/O control register L_3S TIORL_3S
Timer I/O control register H_4S TIORH_4S R/W
Timer I/O control register L_4S TIORL_4S
Timer interrupt enable
register_3S
Timer interrupt enable
register_4S
Timer output master enable
register S
Timer gate control register S
Timer output control register 1S TOCR1S
Timer output control register 2S TOCR2S
Timer counter_3S
Timer counter_4S
Timer cycle data register S
Timer dead time data register S TDDRS
Timer general register A_3S
Timer general register B_3S
Timer general register A_4S
Timer general register B_4S
Register Descriptions
Abbrevia-
tion
TCR_3S
TMDR_3S
TMDR_4S
TIER_3S
TIER_4S
TOERS
TCNT_3S
TCNT_4S
TCR_4S
TGCRS
TCDRS
TGRA_3S
TGRB_3S
TGRA_4S
TGRB_4S
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'C0
H'80
H'00
H'00
H'0000
H'0000
H'FFFF
H'FFFF
H'FFFF
H'FFFF
H'FFFF
H'FFFF
Address
H'FFFFC600
H'FFFFC601
H'FFFFC602
H'FFFFC603
H'FFFFC604
H'FFFFC605
H'FFFFC606
H'FFFFC607
H'FFFFC608
H'FFFFC609
H'FFFFC60A
H'FFFFC60D
H'FFFFC60E
H'FFFFC60F
H'FFFFC610
H'FFFFC612
H'FFFFC614
H'FFFFC616
H'FFFFC618
H'FFFFC61A
H'FFFFC61C
H'FFFFC61E
Access Size
8, 16, 32
8
8, 16
8
8, 16, 32
8
8, 16
8
8, 16
8
8
8
8, 16
8
16, 32
16
16, 32
16
16, 32
16
16, 32
16