DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 548

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.17 Timer Counter Synchronous Start Register (TCSYSTR)
TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 and
MTU2S counters. Note that the MTU2S does not have TCSYSTR.
Rev. 3.00 May 17, 2007 Page 490 of 1582
REJ09B0181-0300
Bit
7
6
Bit Name
SCH0
SCH1
Note:
Initial
Value
0
0
*
Initial value:
Only 1 can be written to set the register.
R/W:
Bit:
R/W
R/(W)* Synchronous Start
R/(W)* Synchronous Start
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
SCH0
7
0
SCH1
6
0
Description
Controls synchronous start of TCNT_0 in the MTU2.
0: Does not specify synchronous start for TCNT_0 in
1: Specifies synchronous start for TCNT_0 in the MTU2
[Clearing condition]
•
Controls synchronous start of TCNT_1 in the MTU2.
0: Does not specify synchronous start for TCNT_1 in
1: Specifies synchronous start for TCNT_1 in the MTU2
[Clearing condition]
•
the MTU2
the MTU2
When 1 is set to the CST0 bit of TSTR in MTU2
while SCH0 = 1
When 1 is set to the CST1 bit of TSTR in MTU2
while SCH1 = 1
SCH2
5
0
SCH3
4
0
SCH4
3
0
R
2
0
-
R/(W)* R/(W)*
SCH3S SCH4S
1
0
0
0