M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 101

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Table 11.2 No. of DMAC transfer cycles
1 .
0
Coefficient j, k
C
(2) DMAC transfer cycles
DMA Request Bit
Transfer unit
8-bit transfers
(BWi = “0”)
16-bit transfers
(BWi = “1”)
No wait
9
0 .
Internal ROM/RAM
8 /
B
Any combination of even or odd transfer read and write addresses is possible. Table 11.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
The DMAC can issue DMA requests using preselected DMA request factors for each channel as trig-
gers.
The DMA transfer request factors include the reception of DMA request signals from the internal periph-
eral functions, software DMA factors generated by the program, and external factors using input from
external interrupt signals.
See the description of the DMAi factor selection register for details of how to select DMA request factors.
DMA requests are received as DMA requests when the DMAi request bit is set to “1” and the channel i
transfer mode select bits are “01” or “11”. Therefore, even if the DMAi request bit is “1”, no DMA request
is received if the channel i transfer mode select bit is “00”. In this case, DMAi request bit is cleared.
Because the channel i transfer mode select bits default to “00” after a reset, remember to set the channel
i transfer mode select bit for the channel to be activated after setting the DMAC related registers. This
enables receipt of the DMA requests for that channel, and DMA transfers are then performed when the
DMAi request bit is set.
The following describes when the DMAi request bit is set and cleared.
0
0
0
k=1
j=1
1
A
8
G
u
7
o r
. g
0 -
Internal Memory
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
u
1
0
p
0
, 2
0
With wait
2
0
k=2
0
j=2
5
Page 88
(DSi = “1”)
(DSi = “0”)
(DSi = “1”)
(DSi = “0”)
Bus width
16-bit
16-bit
SFR area
8-bit
8-bit
k=2
j=2
f o
3
2
9
Access address
No wait
k=2
j=1
Even
Even
Even
Even
Odd
Odd
Odd
Odd
One wait
k=2
j=2
Separate bus
No. of read No. of write No. of read No. of write
cycles
Single-chip mode
—
—
—
—
1
1
1
2
Two waits Three waits Two waits Three waits
External Memory
k=3
j=3
cycles
—
—
—
—
1
1
1
2
k=4
j=4
Memory expansion mode
Microprocessor mode
cycles
1
1
1
1
1
2
2
2
k=3
j=3
Multiplex bus
11. DMAC
cycles
k=4
1
1
1
1
1
2
2
2
j=4