M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 154

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 17.2 Typical transmit/receive timings in clock synchronous serial I/O mode
1 .
0
C
9
0 .
8 /
B
• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected)
0
0
CLKi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CTSi
TxDi
Transmit
register empty
flag (TXEPT)
Transmit interrupt
request bit (IR)
0
Receive enable
bit (RE)
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
RTSi
CLKi
RxDi
Receive complete
flag (Rl)
Receive interrupt
request bit (IR)
1
A
G
8
Shown in ( ) are bit symbols.
u
7
o r
. g
0 -
The above timing applies to the following settings:
u
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
1
Shown in ( ) are bit symbols.
0
p
0
, 2
0
The above timing applies to the following settings:
f
EXT
2
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
0
: frequency of external clock
0
5
“H”
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“1”
“0”
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“H”
“1”
“0”
“1”
“0”
“0”
“0”
“0”
“L”
“1”
“1”
“1”
Transferred from UARTi receive register
Data is set in UARTi transmit buffer register
D
0
Cleared to “0” when interrupt request is accepted, or cleared by software
to UARTi receive buffer register
D
D
Transferred from UARTi transmit buffer register to UARTi transmit register
f o
1
Dummy data is set in UARTi transmit buffer register
0
T
D
3
D
CLK
2
2
1
9
D
D
3
Transferred from UARTi transmit buffer register to UARTi transmit register
2
D
4
D
Tc
3
D
Cleared to “0” when interrupt request is accepted, or cleared by software
5
D
4
D
1 / f
Receive data is taken in
6
D
5
D
EXT
7
D
Stopped pulsing because CTS = “H”
6
D
D
7
0
Tc = TCLK = 2(n + 1) / fi
Read out from UARTi receive buffer register
D
1
fi: frequency of BRGi count source (f
n: value set to BRGi
D
D
2
0
D
D
3
1
Meet the following conditions are met when the CLKi
input before data reception = “H”
17. Clock synchronous serial I/O mode
D
• Transmit enable bit
• Receive enable bit
• Dummy data write to UARTi transmit buffer register
D
4
2
D
5
D
3
D
6
D
4
D
7
D
5
Stopped pulsing because transfer enable bit = “0”
D
0
“1”
“1”
1
D
, f
1
8
, f
D
2
32
)
D
3
D
4
D
5
D
6
D
7