M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 223

MCU 3/5V 0K,PB-FREE 100-QFP

M30800SFP-BL#U5

Manufacturer Part Number
M30800SFP-BL#U5
Description
MCU 3/5V 0K,PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet

Specifications of M30800SFP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30800SFP-BL#U5M30800SFP-BL#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30800SFP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
1
v
J
6
1 .
0
C
Timer B (timer mode, event counter mode)
Timer B (pulse period/pulse width measurement mode)
Stop Mode and Wait Mode
9
0 .
8 /
B
(1) The TBi (i=0 to 5) register indicates the countervalue during counting at any given time. However, the
(1) If the measurement mode select bit setting is changed after counting is started, the timer Bi interrupt
(2) Indeterminate values are transferred to the reload register during the first valid edge input after count-
(3) The counter value is indeterminate when counting is started. Therefore, the timer Bi overflow flag
(4) The timer Bi overflow flag is set to "0" by writting to the timer Bi mode register at or after counting
(1) To exit stop mode by hardware reset, provide an "L" signal input to the RESET pin until main clock
(2) When entering wait mode, the instruction queue reads ahead to instructions following the WAIT in-
(3) When entering stop mode, the instruction lined in the instruction queue is executed before the inter-
0
0
0
1
A
8
G
counter is "FFFF
the counter stops and before the counter starts counting.
request bit is set to "1".
ing is started. The timer Bi interrupt request is not generated at this time.
setting may change to "1" and causes the timer Bi interrupt requests to be generated until a valid edge
is input after counting is started.
timing of the next count source, after the count start flag is set to "1" and the timer Bi overflow flag is
set to "1".
oscillation is stable.
struction, and the program stops. Write at least 4 NOP instructions after the WAIT instruction.
rupt for recovery is done. Write the JMP.B instruction, as follows, after the instruction setting the all
clock stop control bit to "1".
u
7
o r
. g
0 -
LABEL_001:
u
1
0
p
0
, 2
0
2
0
0
5
nop
Page 210
jmp.b LABEL_001
bset 0,prcr
bset 0,cm1
nop
nop
nop
mov.b #0,prcr
16
" when reloading. The setting value can be read after setting the TBi register while
f o
3
2
9
; JMP.B instruction executed (Jump to the next instruction soon
; all clocks stopped (entering stop mode)
; protection removed
; nop(1)
; nop(2)
; nop(3)
; nop(4)
; protection set
; with no instruction between JMP.B and LABEL.)
27. Usage Precaution

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