M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 43

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
7. Bus
7.1 Bus Settings
e
E
1
v
J
Table 7.1 Factors for switching bus settings
6
1 .
0
The BYTE pin, bit 0 to 3 of the external data bus width control register (address 000B
processor mode register 0 (address 0004
0005
Table 7.1 shows the factors used to change the bus settings, Figure 7.1 shows external data bus width
control register and Table 7.2 shows external area 0 to 3 and external area mode.
Switching external address bus width
Switching external data bus width
Switching between separate and multiplex bus
(1) Selecting external address bus width
(2) Selecting external data bus width
(3) Selecting separate/multiplex bus
C
9
0 .
8 /
B
You can select the width of the address bus output externally from the 16 Mbytes address space, the
number of chip select signals, and the address area of the chip select signals. (Note, however, that when
you select “Full CS space multiplex bus”, addresses A
1 of the processor mode register 1 allow you to set the external area mode.
When using DRAM controller, the DRAM area is output by multiplexing of the time splitting of the row and
column addresses.
You can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. When
the data bus width bit of the external data bus width control register is “0”, the data bus width is 8 bits;
when “1”, it is 16 bits. The width can be set for each of the external areas. The default bus width for
external area 3 is 16 bits when the BYTE pin is “L” after a reset, or 8 bits when the BYTE pin is “H” after
a reset. The bus width selection is valid only for the external bus (the internal bus width is always 16 bits).
During operation, fix the level of the BYTE pin to “H” or “L”.
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
0
• Separate bus
• Multiplex bus
0
0
1
16
In this bus configuration, input and output is performed on separate data and address buses. The data
bus width can be set to 8 bits or 16 bits using the external data bus width control register. For all
programmable external areas, P0 is the data bus when the external data bus is set to 8 bits, and P1 is
a programmable IO port. When the external data bus width is set to 16 bits for any of the external
areas, P0 and P1 (although P1 is undefined for any 8-bit bus areas) are the data bus.
When accessing memory using the separate bus configuration, you can select a software wait using
the wait control register.
In this bus configuration, data and addresses are input and output on a time-sharing basis. For areas
for which 8-bit has been selected using the external data bus width control register, the 8 bits D
are multiplexed with the 8 bits A
data bus width control register, the 16 bits D
accessing memory using the multiplex bus configuration, two waits are inserted regardless of whether
you select “No wait” or “1 wait’ in the appropriate bit of the wait control register.
A
8
G
u
7
) are used to change the bus settings.
o r
. g
0 -
u
1
0
p
0
, 2
0
2
0
0
5
____
Bus setting
Page 30
f o
3
2
9
0
to A
7
16
. For areas for which 16-bit has been selected using the external
) and bit 0 and 1 of the processor mode register 1 (address
0
to D
BYTE pin (external area 3 only)
Bits 4 and 5 of processor mode register 0
External data bus width control register
15
0
to A
are multiplexed with the 16 bits A
15
are output.) The combination of bits 0 and
Switching factor
16
), bits 4 and 5 of the
0
to A
15
. When
0
to D
7. Bus
7