M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 351

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
1
6
Version
C
Rev.E
8 /
0
G
o r
Page 250 Figure1.28.23 t
Page 251 Figure 1.28.24 t
Page 252 Figure1.28.25 t
Page 255 Table1.29.1 Power supply (under planning)-->delete, Program/erase voltage
144-pin version description addition
Pages 1, 6 •Supply voltage --> external ROM version addition
Page 7 (3) Package 144P6Q --> 144P6Q-A
Page 21 Figure 1.4.4 (111) Function select register C 00
Page 28 Figure 1.6.2 ROMless version addition
Page 29 Figure 1.6.3 External area 0 to 3 addition
Page 34 Addition
Page 37 Figure 1.7.4 Input RDY signal at i + 1 cycles for i wait --> RDY signal received timing
Page 46 Figure 1.8.4 System clock control register 0 CM0 --> contents of the Function
Page 48 On the second line from the bottom, 'Although stop mode ... must be set to "1".'
Page 49 Table 1.8.4 CS0 to CS3 --> CS0 to CS3, BHE
Page 52 Table 1.8.6 CM0i: Clock control register 0 (address 0006
Page 60 • Vector table dedicated for emulator
Page 69 Interrupt priority
Page 75 (6) Explanation of No.1 and No. 2 are partly revised.
Page 76, 77 From "• To return from an interrupt..." to the end of page 77 --> addition
Page 78 "In the stop...released." on the third line from the bottom --> addition
Page 79 Figure 1.10.2 Notes 10, 11 --> addition
Page 87 Figure 1.11.6 is partly revised.
Page 88 Table for "Coefficient j, k" is partly revised.
Page 89 Figure 1.11.7 is partly revised.
Page 90 Explanation of (3) is partly revised.
Page 94 Figure 1.13.3 Timer Ai register -->Notes 2 to 4 addition, •Pulse width modulation
Page 97 Figure 1.13.6 --> change
Page 98 Table 1.13.3 --> Note 2 addition, •Normal processing operation --> •Normal pro-
Page 99 Figure 1.13.7 Timer Ai mode register (When using two-phase pulse signal process-
u
Similarly, page 202 Figures 1.26.11 When reset ?0000??? --> 00000X0X
p
f(X
for i wait: i +1
changed, Notes 10, 11 addition
-->addition
--> WR, WRL, WRH, DW, CASL
division register (address 000C
'the interrupt that a request came to most in the first place is accepted at first, and
then,' --> delete
mode (8-bit PWM) --> Values that can be set is changed, Up/down flag --> Note addi-
tion
cessing operation (Timer A2 and timer A3), •Multiply-by-4 processing operation -->
•Multiply-by-4 processing operation (Timer A3 and timer A4)
IN
_______
Interrupt vector address (address 000020
000020
)-->f(
_______
BCLK
16
to 000022
), 2.7V-5.5V-->delete
_______
(119) Function select register B3 ?0000??? --> 00000X0X
Figures 1.26.12 When reset 00
h(BCLK-DB)
d(CAS-RAS)
d(DB-CAS)
_______
______
16
)
_________
-->t
-->t
-->t
_______
Contents for change
16
su(DB-CAS)
h(CAS-DB)
su(CAS-RAS)
) bit i --> addition
_______
C- 9
, t
_______
h(BCLK-CAS)-->
16
--> 0XXXXXX0
16
16
_______ _______
WR, BHE, WRL, WRH, W, CASL
--> 0XXXXXX0
to 000023
t
h(BCLK-DB)
_______
16
) bit i, MCDi: Main clock
_______
16
)-->... (address
_______
___
_________
Revision History
09/02/'01
Revision
date