M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 161

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 18.2 Typical transmit timings in UART mode
1 .
0
C
9
0 .
8 /
B
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
CTSi
TxDi
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
0
0
0
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
1
A
8
G
u
7
o r
. g
0 -
u
1
Shown in ( ) are bit symbols.
0
p
0
, 2
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
0
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
2
The above timing applies to the following settings :
0
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = “0”.
0
“H”
5
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
Page 148
ST
Start
Start
ST
bit
bit
Data is set in UARTi transmit buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
D
f o
D
0
Data is set in UARTi transmit buffer register.
0
D
3
D
1
2
1
Tc
9
D
D
2
2
D
D
3
3
D
Tc
D
4
4
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Transferred from UARTi transmit buffer register to UARTi transmit register
D
D
5
5
D
D
6
6
D
Transferred from UARTi transmit buffer register to UARTi transmit register
D
18. Clock asynchronous serial I/O (UART) mode
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
Parity
7
7
bit
P
D
fi : frequency of BRGi count source (f
f
n : value set to BRGi
8
EXT
Stop
Cleared to “0” when interrupt request is accepted, or cleared by software
bit
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
SP
SP
Stop
bit
: frequency of BRGi count source (external clock)
SP
fi : frequency of BRGi count source (f
f
n : value set to BRGi
EXT
ST
Stop
bit
: frequency of BRGi count source (external clock)
D
ST
0
D
1
D
0
D
2
D
1
D
Stopped pulsing because transmit enable bit = “0”
3
D
2
EXT
D
4
D
3
D
5
D
EXT
4
D
1
6
, f
D
5
8
D
, f
7
D
32
6
1
P SP
)
, f
D
8
7
, f
32
D
8
)
SPSP
ST
D
ST
0
D
D
1
0
D
1