M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 246

MCU 3/5V 0K,PB-FREE 100-QFP

M30800SFP-BL#U5

Manufacturer Part Number
M30800SFP-BL#U5
Description
MCU 3/5V 0K,PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet

Specifications of M30800SFP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30800SFP-BL#U5M30800SFP-BL#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30800SFP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
1
v
J
6
Switching characteristics (referenced to V
Table 28.20 Memory expansion mode and microprocessor mode
Note 1: Calculated according to the BCLK frequency as follows:
1 .
0
t
t
t
t
t
t
t
t
t
t
t
C
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
h(WR-AD)
h(WR-CS)
d(BCLK-ALE)
h(BCLK-ALE)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(DB-WR)
h(WR-DB)
w(WR)
9
0 .
8 /
Symbol
B
0
0
0
1
A
G
8
u
7
o r
. g
0 -
t
t
t
t
t
d(DB – WR)
h(WR – DB)
h(WR – AD)
h(WR – CS)
w( WR)
u
1
0
p
0
, 2
(with wait, accessing external memory)
0
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
ALE signal output hold time
RD signal output hold time
Data output hold time (WR standard)
WR signal width
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
ALE signal output delay time
RD signal output delay time
WR signal output hold time
Data output delay time (WR standard)
Chip select output delay time
WR signal output delay time
2
specified)
0
=
0
5
f
=
=
=
=
(BCLK)
10 X n
Page 233
10 X n
9
f
f
f
f
(BCLK)
(BCLK)
(BCLK)
(BCLK)
9
X 2
10
10
10
9
9
9
X 2
X 2
X 2
Parameter
– 15
f o
– 20
3
2
– 10
– 10
– 10
9
[ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)
[ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively)
[ns]
[ns]
[ns]
CC
= 5V, V
SS
Measuring condition
= 0V at Topr = 25
Figure 28.1
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
28. Electrical characteristics
Min.
– 5
– 3
– 3
– 3
– 2
o
0
0
Standard
C unless otherwise
Max.
18
18
18
10
18
V
CC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 5V

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