M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 141

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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6
Figure 16.4 Block diagram of UARTi (i = 2 to 4) transmit/receive unit
1 .
0
C
RxDi
9
0 .
8 /
B
0
0
0
1
A
8
G
u
7
o r
. g
0 -
SP
u
1
SP
0
p
0
, 2
0
reverse circuit
2SP
1SP
2
RxD data
SP
0
0
5
0
2SP
1SP
SP
Page 128
0
PAR
PAR
No reverse
Reverse
0
PAR
disabled
PAR
enabled
“0”
PAR
enabled
PAR
disabled
f o
0
3
UART
Clock
synchronous
type
2
Clock
synchronous
type
UART
9
0
0
UART
(9 bits)
UART
(9 bits)
0
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
D
D
8
8
Data bus high-order bits
Data bus low-order bits
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART(7 bits)
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
D
D
UART(7 bits)
7
7
Error signal output
disable
Error signal output
enable
D
D
6
6
D
D
output circuit
Error signal
5
5
D
D
4
4
UARTi transmit register
UARTi receive register
D
D
No reverse
3
3
Reverse
D
D
SP
PAR : Parity bit
i
2
2
reverse circuit
TxD data
D
D
: Stop bit
: 2 to 4
1
1
D
D
0
0
16. Serial I/O
Address 033A
Address 033B
Address 032A
Address 032B
Address 02FA
Address 02FB
Address 033E
Address 033F
Address 032E
Address 032F
Address 02FE
Address 02FF
UART2 transmit
buffer register
UARTi receive
buffer register
TxDi
16
16
16
16
16
16
16
16
16
16
16
16