M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 103

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
Precautions for DMAC
e
E
1
v
J
6
1 .
0
C
(1) Do not clear the DMA request bit of the DMAi request cause select register.
(2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select
(3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to
9
0 .
8 /
B
(4) Recommended procedure for starting DMA transfer
0
0
In M16C/80, when a DMA request is generated while the channel is disabled (Note), the DMA transfer is
not executed and the DMA request bit is cleared automatically.
Note :The DMA is disabled or the transfer count register is "0".
register to "1" simultaneously using the OR instruction.
the DMA request bit, simultaneously. In this case, set the corresponding DMA channel to disabled
before changing the DMAi request cause select bit. At least 26 cycles are needed from the instruction
to write to the DMAi request cause select register to enable DMA.
0
1
dummy_loop:
A
8
G
Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer after
u
7
o r
. g
0 -
e.g.) OR.B #0A0h, DMiSL
•When writing to the DMAi request cause register including overwriting the same value to the
1. Disable the corresponding channel i DMA in DMA mode registers 0 and 1.
2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral
3. Set the DMAi request cause select register. At this time, write a '1' to the DMA request
u
1
0
DMAi request cause register;
should remain disabled at this time. For example, when using UART0 transmit, disable
UART0 transmit.
bit (bit 7)
p
0
, 2
0
push.w
stc
and.b
ldc
mov.b
push.w
mov.w
sbjnz.w
pop.w
or.b
ldc
pop.w
2
0
DMA initial setting
0
5
Page 90
R0
DMD0, R0
#11111100b, R0L
R0, DMD0
#10000011b, DM0SL ; Select timer A0
R0
#6,R0
#1,R0,dummy_loop
R0
#00000001b, R0L
R0, DMD0
R0
f o
3
2
9
; DMiSL is DMAi request cause select register
; Store R0 register
; Read DMA mode register 0
; Clear DMA0 transfer mode select bit to "00"
; DMA0 disabled
; (Write "1" to DMA request bit simultaneously)
; Store R0 register
;
; Dummy cycle
; Restore R0 register
; Set DMA0 single transfer
; DMA0 enabled
; Restore R0 register
At least 26 cycles are needed
until DMA enabled.
11. DMAC