M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 48

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
Table 7.5 Operation of RD, WRL, and WRH signals
Note: It becomes WR signal.
Table 7.6 Operation of RD, WR, and BHE signals
6
1 .
0
(3) Read/write signals
C
Data bus width
9
Data bus width
0 .
8 /
With a 16-bit data bus, bit 2 of the processor mode register 0 (address 0004
RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the
combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode
register 0 (address 0004
data bus area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the
processor mode register 0 (address 0004
Tables 7.5 and 7.6 show the operation of these signals.
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 0004
Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals.
B
_____
0
0
0
1
16-bit
8-bit
A
16-bit
G
8
8-bit
________
u
7
o r
. g
0 -
u
1
register (address 000A
0
p
0
, 2
0
2
0
0
______
5
______
_____
Page 35
RD
H
H
H
H
L
L
L
L
_____
______
RD
H
H
H
H
_____
L
L
_____
_____ _________
______
16
______
________
).) When using both 8-bit and 16-bit data bus widths and you access an 8-bit
f o
WR
________
H
H
H
H
L
L
L
L
3
H (Note)
16
L (Note)
_____
2
________
WRL
9
) to “1”.
H
H
L
L
________
________
_________
_________
Not used
Not used
BHE
H
H
L
L
L
L
16
16
Not used
Not used
).
) has been set (Note).
WRH
H
H
L
L
_________
H / L
H / L
_____
A0
H
H
L
L
L
L
Read data
Write 1 byte of data to odd address
Write data to both even and odd addresses
Write 1 byte of data to even address
Write 1 byte of data
Read 1 byte of data
______
Write 1 byte of data to odd address
Write 1 byte of data
Read 1 byte of data
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
________
Status of external data bus
Status of external data bus
_____
16
________
) select the combinations of
_________
7. Bus