M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 166

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 19.2 Output timing of the parity error signal
Figure 19.3 SIM interface format
1 .
0
C
9
0 .
8 /
B
0
0
(a) Function for outputting a parity error signal
(b) Direct format/inverse format
0
1
A
During reception, with the error signal output enable bit (bit 7 of address 033D
assigned “1”, you can output an “L” level from the TxD
receive buffer register is read while outputting a parity error signal, the parity error flag is cleared to "0"
and at the same time the TxDi output is returned high. And during transmission, comparing with the
case in which the error signal output enable bit (bit 7 of address 033D
"0", the transmission completion interrupt occurs in the half cycle later of the transfer clock. Therefore
parity error signals can be detected by a transmission completion interrupt program. Figure 19.2
shows the output timing of the parity error signal.
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D
output from TxDi.
Figure 19.3 shows the SIM interface format.
G
8
u
7
o r
. g
0 -
complete flag
u
1
0
p
0
, 2
• LSB first
0
2
Transfer
Receive
0
(inverse)
Transfer
0
(direct)
5
clock
RxD
TxD
clcck
TxD
TxD
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19. Clock-asynchronous serial I/O mode (compliant with the SIM interface)
i
i
i
i
0
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
data is output from TxDi. If you choose the inverse format, D
f o
3
2
9
ST
D0
D0
D7
D1
D1
D6
D2
D2
D5
D3
D3
D4
Hi-Z
i
pin when a parity error is detected. If the UARTi
D4
D4
D3
D5
D5
D2
D6
D6
D1
16
ST : Start bit
P : Even Parity
SP : Stop bit
D7
D7
D0
, 032D
P
P
P
16
P : Even parity
, 02FD
SP
7
16
data is inverted and
, 032D
16
) is assigned
16
, 02FD
16
)