M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 289

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 30.1 Flash memory control registers
1 .
0
C
Figure 30.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 30.3 shows a flowchart
for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.
9
0 .
8 /
B
0
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Flash memory control register 0
0
b7 b6 b5 b4 b3 b2 b1 b0
1
A
8
G
0
u
7
o r
. g
0 -
0
u
1
0
p
0
, 2
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently
Note 4: Use the control program except in the internal flash memory for write to this bit.
Note : For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
0
0
0
2
0
0
5
0
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit. Also write to this
bit when NMI pin is "H" level.
when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not
enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
after setting it to 1 (reset).
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succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit.
During parallel I/O mode,programming,erase or read of flash memory is not controlled by
this bit,only by external pins.
0
0
Bit symbol
Reserved bit
Reserved bit
FMR13
Reserved bit
Bit symbol
FMR00
FMR01
FMR02
FMR03
FMR05
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
f o
3
Symbol
2
Symbol
FMR1
9
FMR0
Flash memory power
supply-OFF bit (Note)
RY/BY status flag
CPU rewrite mode
select bit (Note 1)
Lock bit disable bit
(Note 2)
User ROM area select bit (
Note 4) (Effective in only
boot mode)
Flash memory reset bit
(Note 3)
Bit name
Bit name
Address
Address
0376
0377
16
16
0: Flash memory power supply is
1: Flash memory power supply-off
Must always be set to “0”
Must always be set to “0”
0: Busy (being written or erased)
1: Ready
0: Normal mode
1: CPU rewrite mode
0: Block lock by lock bit data is
1: Block lock by lock bit data is
0: Normal operation
1: Reset
Must always be set to “0”
0: Boot ROM area is accessed
1: User ROM area is accessed
When reset
XXXX0XXX
When reset
connected
(Software commands invalid)
(Software commands acceptable)
XX000001
enabled
disabled
2
2
Function
Function
30. CPU Rewrite Mode
R
R W
R
R W
W
W