M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 251

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
1 .
Figure 28.3 V
0
C
9
0 .
8 /
B
Memory expansion Mode and Microprocessor Mode (with 1 wait)
0
BCLK
ALE
CSi
ADi
BHE
RD
DB
BCLK
ALE
CSi
ADi
BHE
WR,WRL,
WRH
DBi
0
0
Read Timing
Write Timing
1
A
8
G
u
7
o r
. g
0 -
*3:It depends on operation frequency.
u
1
0
p
0
, 2
t
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
t
t
t
t
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
0
d(DB-WR)
h(WR-DB)
h(WR-AD)
h(WR-CS)
w(WR)
*1:It is a guarantee value with being alone. 35ns.max garantees as t
*2:It depends on operation frequency.
t
2
CC
d(BCLK-AD)
t
0
d(BCLK-ALE)
t
18ns.max
0
d(BCLK-ALE)
=5V timing diagram (2)
18ns.max
=(tcyc/2 x n-15)ns.min
t
t
5
ac2(RD-DB)
ac2(AD-DB)
t
t
t
=(tcyc x n-20)ns.min
=(tcyc/2-10)ns.min
=(tcyc/2-10)ns.min
=(tcyc/2-10)ns.min
10ns.max
18ns.max
d(BCLK-AD)
Page 238
d(BCLK-CS)
18ns.max*1
18ns.max*1
t
18ns.max
d(BCLK-CS)
d(BCLK-RD)
tcyc
tcyc
=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
t
h(BCLK-ALE)
f o
t
18ns.max
-2ns.min
t
d(BCLK-WR)
-2ns.min
h(BCLK-ALE)
Hi-Z
3
2
t
9
ac2(AD-DB)*2
t
t
d(DB-WR)*3
ac2(RD-DB)*2
t
w(WR)*3
t
su(DB-BCLK)
26ns.min*1
t
t
t
t
h(BCLK-WR)
h(WR-DB)*3
h(WR-CS)*3
h(WR-AD)*3
-3ns.min
Measuring conditions
t
h(BCLK-AD)
• V
• Input timing voltage
• Output timing voltage
t
h(BCLK-RD)
t
t
t
-5ns.min
h(BCLK-AD)
h(BCLK-CS)
-3ns.min
0ns.min
h(BCLK-CS)
-3ns.min
CC
-3ns.min
t
t
t
-3ns.min
h(RD-CS)
h(RD-AD)
h(RD-DB)
=5V±10%
0ns.min
d(BCLK-AD)
0ns.min
:Determined with V
:Determined with V
28. Electrical characteristics
+t
su(DB-BCLK)
IH
OH
.
=2.5V, V
=2.0V, V
Vcc=5V
IL
OL
=0.8V
=0.8V