M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 346

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
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6
Version
Rev.C1
Rev.C2
REV.C
C
8 /
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G
o r
Page 58 Table 1.9.3 Software interrupt number 40,41, Add fault error, Add Note 2
Page 59 Interrupt control register Line 4 delate
Page 64 Interrupt sequence (1)
Page 66 Saving registers Last line added
Page 67 Interrupt Priority
Page 72 (2) Setting the stack pointer Last line added
Page 74 Watchdog timer Line 2
Page 75 Figure 75 System clock control register 0 added
Page 97 Figure 1.13.9
Page 181 Figure 1.25.4
Page 182 Figure 1.25.5
Page 131 Figure 1.16.12
Page 135 Table 1.17.3
Page 132 Table 1.18.3
Page 147 Figure 1.19.1
Page 153
Page 154 Figure 1.20.3
Page 159 Clock phase setting
Page 171 Line 3
Page 171 Figure 1.22.2
Page 176 Figure 1.24.3 added
Page 178 Figure 1.25.1
Page 200 Table 1.26.2 and 1.26.3 and Figure 1.26.14
Page 204-
Page 214 Table 1.28.22
Page 220 Figure 1.28.6
Page 223 Figure 1.28.9
Page 24 Line 3
Page 161 Note 2:
Page 18 Figure 1.4.3
Page 19 Figure 1.4.4
Page 22 Figure 1.5.3
u
p
A watchdog timer interrupt is generated when --> Whether a watchdog timer interrupt
is generated or reset is selected when
Last part :Watchdog timer function select bit is initialized only at reset. After reset,
watchdog timer interrupt is selected. added
UARTi transmission-reception control register 0 ..., whereas UARTi special mode
register 3 ... --> Bit 6 of UARTi transmission-reception control register 0 ..., whereas
bit 1 of UARTi special mode register 3 ...
Line 15
... output is high impedance. --> ... output is indeterminate.
input mode. added
CNVss is added
same ...
When f(X
addition
Bit 4 overflow --> underflow
Electric characteristics added
IN
) is over 10 MHz, the f
Set the function select register A to I/O port and the direction register to
A software reset has almost the same ... --> A software reset has the
t
*1 delated, Last line added
Count value
Both register Note2 added
RxDi bit 1 and 6 at address 03C7
RxDi bit 1 and 6 at address 03C7
Upper figure changed, note added
overflow --> underflow
Note delate
When reset --> indeterminate, Note 4 is added.
t
WR, WRL, WRH(sepalate bus) wave change
(60) Timer B3,4,5 count start flag value change
Flash memory control register 0 and 1 added
Flash memory control register 0 and 1 added
h(BCLK-DW)
h(BCLK-CAS)
Contents for change
add
AD
--> t
frequency must be under 10 MHz by dividing. -->
h(BCLK-DW)
C - 4
16
16
--> bit 1 and 7 ...
--> bit 1 and 7 ...
Revision History
Revision
99.5.12
99.5.20
99.6.4
99.7.6
date