M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 247

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Switching characteristics (referenced to V
Table 28.21 Memory expansion mode and microprocessor mode
1 .
Note 1: Calculated according to the BCLK frequency as follows:
0
C
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
h(WR-AD)
h(WR-CS)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-ALE)
h(BCLK-ALE)
d(AD-ALE)
h(ALE-AD)
dz(RD-AD)
h(BCLK-DB)
9
d(BCLK-WR)
h(BCLK-WR)
d(DB-WR)
h(WR-DB)
0 .
8 /
Symbol
B
0
0
0
1
A
8
G
u
7
o r
. g
0 -
t
t
t
t
t
t
t
t
d(AD – ALE)
h(ALE – AD)
h(RD – AD)
h(RD – CS)
h(WR – AD)
h(WR – CS)
d(DB – WR)
h(WR – DB)
u
1
0
p
0
, 2
0
(with wait, accessing external memory, multiplex bus area selected)
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output hold time
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
RD signal output delay time
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (address standard)
ALE signal output hold time (address standard)
Address output flowting start time
Data output hold time (BCLK standard)
Chip select output delay time
Data output delay time (WR standard)
Data output hold time (WR standard)
WR signal output delay time
WR signal output hold time
2
specified)
0
0
5
=
=
=
=
=
=
=
=
Page 234
10 X m
f
f
f
f
f
f
f
f
(BCLK)
(BCLK)
(BCLK)
(BCLK)
(BCLK)
(BCLK)
(BCLK)
(BCLK)
9
10
10
10
10
10
10
10
Parameter
f o
9
9
9
9
9
9
9
X 2
X 2
X 2
X 2
X 2
X 2
X 2
X 2
3
2
9
– 25
– 23
– 10
– 10
– 10
– 10
– 10
– 10
[ns]
[ns]
[ns]
[ns]
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
[ns]
[ns]
[ns]
CC
= 5V, V
SS
= 0V at Topr = 25
Measuring condition
Figure 28.1
28. Electrical characteristics
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
o
Min.
C unless otherwise
– 2
-3
-3
-5
-3
-5
Standard
Max.
18
18
18
18
18
8
V
CC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 5V