M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 156

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 17.5 The transfer clock output from the multiple pins function usage
Figure 17.6 Serial data logic switch timing
1 .
0
C
9
0 .
8 /
B
0
0
(c) Transfer clock output from multiple pins function (UART1)
(d) Continuous receive mode
(e) Separate CTS/RTS pins function (UART0)
(f) Serial data logic switch function (UART2 to UART4)
0
1
A
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the port function select register (bits of related to-P6
multiple pins function is valid only when the internal clock is selected for UART1. Note that when this
function is selected, UART1 CTS/RTS function cannot be used.
If the continuous receive mode enable bit (bits 2 and 3 at address 0370
032D
receive buffer register is read out, the unit simultaneously goes to a receive enable state without
having to set dummy data to the transmit buffer register back again.
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
When the data logic select bit (bit6 at address 033D
buffer register or reading from receive buffer register, data is reversed. Figure 17.6 shows the ex-
ample of serial data logic switch timing.
G
8
u
7
o r
. g
0 -
u
Transfer clock
1
0
•When LSB first
p
0
16
, 2
0
(no reverse)
, 02FD
2
0
(reverse)
Note: This applies when the internal clock is selected and transmission
0
5
_______ _______
Microcomputer
TxD
TxD
Page 143
16
is performed only in clock synchronous serial I/O mode.
CLKS
) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the
CLK
i
i
T
X
“H”
“H”
“H”
D
“L”
“L”
“L”
1
1
1
(P6
(P6
(P6
f o
7
5
4
)
)
)
3
2
_______ _______
9
D0
D0
D1
D1
IN
CLK
D2
D2
D3
D3
16
, 032D
17. Clock synchronous serial I/O mode
D4
D4
16
, 02FD
D5
D5
4
IN
CLK
and P6
16
D6
D6
) = “1”, and writing to transmit
16
5
, bit 5 at address 033D
). (See Figure 17.5) The
D7
D7
16
,