M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 77

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
Figure 9.4 Exit priority register
6
1 .
0
C
9
0 .
8 /
B
0
0
b7
Exit priority register
0
9.7 Interrupt Enable Flag (I Flag)
9.8 Interrupt Request Bit
9.9 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
1
A
8
G
The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set
(= 1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag
is automatically cleared to 0 after a reset is cleared.
This bit is set (= 1) by hardware when an interrupt request is generated. The bit is cleared to 0 by
hardware when the interrupt request is acknowledged and jump to the interrupt vector.
This bit can be cleared to 0 (but cannot be set to 1) in software.
Interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. When
an interrupt request is generated, the interrupt priority level of this interrupt is compared with the
processor interrupt priority level (IPL). This interrupt is enabled only when its interrupt priority level is
greater than the processor interrupt priority level (IPL). This means that you can disable any particu-
lar interrupt by setting its interrupt priority level to 0.
b6
u
7
o r
. g
0 -
u
b5
1
0
p
0
, 2
0
b4
2
0
b3
0
5
b2
Page 64
b1
b0
Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is
Note 2: Set to the same value as the processor interrupt priority level (IPL) set in
Note 3: The high-speed interrupt can only be specified for interrupts with
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Bit symbol
f o
RLVL1
RLVL2
RLVL0
FSIT
Symbol
RLVL
3
2
higher than that set in the exit priority register.
the flag register (FLG).
interrupt priority level 7. Specify interrupt priority level 7 for only one
interrupt.
9
Interrupt priority set bit for
exiting Stop/Wait state
(Note 1,2)
High-speed interrupt
set bit (Note 3)
name
Bit
Address
009F
16
When reset
XXXX0000
0: Interrupt priority level 7 = normal
1: Interrupt priority level 7 = high-speed
b2 b1 b0
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
interrupt
interrupt
2
Function
9. Interrupt Outline
R
W