M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 61

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
8.4 Stop Mode
e
E
1
v
J
Table 8.2 Clock output setting (single chip mode)
Table 8.3 Clock output setting (memory expansion/microprocessor mode)
6
Note :Must use P5
1 .
BCLK output function
0
Writing “1” to the all-clock stop control bit (bit 0 at address 0007
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that V
mains above 2V.
Because the oscillation of BCLK, f
functions such as the A/D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 8.4 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt.
When using an interrupt to exit stop mode, the relevant interrupt must have been enabled and set to a
priority level above the level set by the interrupt priority set bits (bits 2, 1, and 0 at address 009F
exiting a stop/wait state. Set the interrupt priority set bits for the exit from a stop/wait state to the same level
as the flag register (FLG) processor interrupt level (IPL). Figure 8.6 shows the exit priority register.
The priority level of the interrupt which is not used to cancel stop mode, must have been changed to 0.
When exiting stop mode using an interrupt, the relevant interrupt routine is executed.
If only a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all
interrupt to 0, then shift to stop mode.
When shifting to stop mode and reset, the main clock division register (000C
C
BCLK output function
9
0 .
8 /
B
0
0
0
1
select bit
A
8
G
PM07
select bit
Ignored
u
7
PM07
0/1
o r
. g
0 -
1
1
1
0
1
1
1
1
u
1
0
p
0
, 2
0
2
0
0
5
7
Page 48
as input port.
Clock output function select
Clock output function select
CM01
CM01
0
0
1
1
0
0
0
1
1
0
f o
______
3
bit
bit
2
1
9
to f
CM00
CM00
32
0
1
0
1
0
0
1
0
1
0
, f
1SIO2
to f
Ignored
Ignored
Ignored
Ignored
PM15
PM15
32SIO2
ALE pin select bit
ALE pin select bit
0
1
1
0
, fc, fc
Ignored
Ignored
Ignored
Ignored
PM14
PM14
16
32
0
0
1
1
) stops all oscillation and the microcom-
, and f
AD
BCLK output
f
"L" output (not P5
fc output
f
ALE output
fc output
f
f
P5
32
8
8
32
stops in stop mode, peripheral
8. Clock Generating Circuit
output
P5
output
P5
3
16
output
output
I/O port
3
3
) is set to “08
/BCLK/ALE/CLK
/BCLK/ALE/CLK
pin function
pin function
(Note)
(Note)
(Note)
3
16
)
”.
OUT
OUT
16
CC
) for
re-