DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 116

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Exception Handling
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
Note: * Supported only by the H8S/2268 Group.
4.6
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
2. The interrupt mask bit is updated and the T bit * is cleared.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR * after execution of trap instruction exception
handling.
Table 4.4
Legend:
1:
0:
—: Retains value prior to execution
Note: * Supported only by the H8S/2268 Group.
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REJ09B0071-0500
from the vector table to the PC, and program execution begins from that address.
register (EXR) * are saved to the stack.
from the vector table to the PC, and program execution starts from that address.
Interrupt Control Mode
Set to 1
Cleared to 0
Trap Instruction
Status of CCR and EXR * after Trap Instruction Exception Handling
0
2 *
1
1
I
CCR
UI
—
—
I2 to I0
—
—
EXR *
—
T
0