DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 44

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 13.32 Retransfer Operation in SCI Receive Mode ........................................................... 372
Figure 13.33 Example of Reception Processing Flow................................................................. 372
Figure 13.34 Timing for Fixing Clock Output Level................................................................... 373
Figure 13.35 Clock Halt and Restart Procedure .......................................................................... 374
Figure 13.36 Example of Clocked Synchronous Transmission by DTC ..................................... 377
Figure 13.37 Sample Flowchart for Mode Transition during Transmission................................ 379
Figure 13.38 Asynchronous Transmission Using Internal Clock ................................................ 379
Figure 13.39 Synchronous Transmission Using Internal Clock .................................................. 380
Figure 13.40 Sample Flowchart for Mode Transition during Reception ..................................... 380
Figure 13.41 Operation when Switching from SCK Pin Function to Port Pin Function ............. 381
Figure 13.42 Operation when Switching from SCK Pin Function to Port Pin Function
Section 14 I
Figure 14.1 Block Diagram of I
Figure 14.2 I
Figure 14.3 I
Figure 14.4 I
Figure 14.5 I
Figure 14.6 Flowchart for IIC Initialization (Example)............................................................. 408
Figure 14.7 Flowchart for Master Transmit Mode (Example)................................................... 409
Figure 14.8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0).......... 411
Figure 14.9 Example of Master Transmit Mode Stop Condition Generation Timing
Figure 14.10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
Figure 14.11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)
Figure 14.12 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0,
Figure 14.13 Example of Master Receive Mode Stop Condition Generation Timing
Figure 14.14 Flowchart for Slave Transmit Mode (Example)..................................................... 418
Figure 14.15 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) ....... 420
Figure 14.16 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) ....... 421
Figure 14.17 Sample Flowchart for Slave Transmit Mode.......................................................... 422
Figure 14.18 Example of Slave Transmit Mode Operation Timing (MLS = 0) .......................... 424
Figure 14.19 IRIC Setting Timing and SCL Control................................................................... 425
Figure 14.20 Block Diagram of Noise Cancellor ........................................................................ 427
Figure 14.21 Points for Attention Concerning Reading of Master Receive Data........................ 433
Rev. 5.00 Sep. 01, 2009 Page xlii of l
REJ09B0071-0500
(Example of Preventing Low-Level Output).......................................................... 382
(MLS = WAIT = 0) ................................................................................................ 412
(Example)............................................................................................................... 413
(Example)............................................................................................................... 414
WAIT = 1).............................................................................................................. 416
(MLS = ACKB = 0, WAIT = 1)............................................................................. 417
2
2
2
2
C Bus Interface Connections (Example: This LSI as Master) ............................. 386
C Bus Data Formats (I
C Bus Data Format (Clocked Synchronous Serial Format) ................................. 406
C Bus Timing....................................................................................................... 407
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
2
C Bus Interface....................................................................... 385
2
C Bus Formats) ............................................................... 406