DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 392

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
13.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the 8th
pulse of the basic clock as shown in figure 13.6. Thus, the reception margin in asynchronous mode
is given by formula (1) below.
Where M: Reception margin (%)
Assuming values of F (absolute value of clock rate deviation) = 0, D (clock duty) = 0.5, and N
(ratio of bit rate to clock) = 16 in formula (1), the reception margin can be given by the formula.
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Rev. 5.00 Sep. 01, 2009 Page 340 of 656
REJ09B0071-0500
M = | (0.5 –
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 13.6 Receive Data Sampling Timing in Asynchronous Mode
2N
1
) – (L – 0.5) F –
0
8 clocks
Start bit
16 clocks
7
|
D – 0.5
N
|
15 0
(1 + F) | × 100 [%]
D0
7
... Formula (1)
15 0
D1