DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 43

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Figure 13.1 Block Diagram of SCI_0........................................................................................ 305
Figure 13.2 Block Diagram of SCI_1 or SCI_2 ........................................................................ 306
Figure 13.3 Example of Internal Base Clock when Average Transfer Rate Is Selected (1) ...... 336
Figure 13.4 Example of Internal Base Clock when Average Transfer Rate Is Selected (2) ...... 337
Figure 13.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Figure 13.6 Receive Data Sampling Timing in Asynchronous Mode ....................................... 340
Figure 13.7 Relationship between Output Clock and Transfer Data Phase
Figure 13.8 Sample SCI Initialization Flowchart ...................................................................... 342
Figure 13.9 Example of Operation in Transmission in Asynchronous Mode (Example
Figure 13.10 Sample Serial Transmission Flowchart .................................................................. 344
Figure 13.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
Figure 13.12 Sample Serial Reception Data Flowchart (1) ......................................................... 347
Figure 13.12 Sample Serial Reception Data Flowchart (2) ......................................................... 348
Figure 13.13 Example of Communication Using Multiprocessor Format (Transmission of
Figure 13.14 Sample Multiprocessor Serial Transmission Flowchart ......................................... 351
Figure 13.15 Example of SCI Operation in Reception (Example with 8-Bit Data,
Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (1)......................................... 353
Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (2)......................................... 354
Figure 13.17 Data Format in Synchronous Communication (For LSB-First) ............................. 355
Figure 13.18 Sample SCI Initialization Flowchart ...................................................................... 356
Figure 13.19 Sample SCI Transmission Operation in Clocked Synchronous Mode ................... 357
Figure 13.20 Sample Serial Transmission Flowchart .................................................................. 358
Figure 13.21 Example of SCI Operation in Reception ................................................................ 359
Figure 13.22 Sample Serial Reception Flowchart ....................................................................... 360
Figure 13.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ....... 362
Figure 13.24 Schematic Diagram of Smart Card Interface Pin Connections............................... 363
Figure 13.25 Normal Smart Card Interface Data Format ............................................................ 364
Figure 13.26 Direct Convention (SDIR = SINV = O/E = 0) ....................................................... 364
Figure 13.27 Inverse Convention (SDIR = SINV = O/E = 1)...................................................... 364
Figure 13.28 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372
Figure 13.29 Retransfer Operation in SCI Transmit Mode ......................................................... 368
Figure 13.30 TEND Flag Generation Timing in Transmission Operation .................................. 369
Figure 13.31 Example of Transmission Processing Flow............................................................ 370
Parity, Two Stop Bits) ............................................................................................ 338
(Asynchronous Mode)............................................................................................ 341
with 8-Bit Data, Parity, One Stop Bit) ................................................................... 343
One Stop Bit).......................................................................................................... 345
Data H'AA to Receiving Station A) ....................................................................... 350
Multiprocessor Bit, One Stop Bit).......................................................................... 352
Times the Transfer Rate)........................................................................................ 366
Rev. 5.00 Sep. 01, 2009 Page xli of l
REJ09B0071-0500