DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 440

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2
Section 14 I
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
2
14.3.1
I
C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF. When TDRE is 1 and the transmit
buffer is empty, TDRE shows that the next transmit data can be written from the CPU. When
RDRF is 1, it shows that the valid receive data is stored in the receive buffer.
2
If I
C is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following
transmission/reception of one frame of data using ICDRS, data is transferred automatically from
2
ICDRT to ICDRS. If I
C is in receive mode and no previous data remains in ICDRR (the RDRF
flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred
automatically from ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is
undefined after a reset.
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
Rev. 5.00 Sep. 01, 2009 Page 388 of 656
REJ09B0071-0500