DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 308

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.12 Contention between TCNT Write and Overflow/Underflow
In the H8S/2268 Group, if there is an up-count or down-count in the T2 state of a TCNT write
cycle and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag
in TSR is not set.
In the H8S/2264 Group, if there is an up-count in the T2 state of a TCNT write cycle and overflow
occurs, the TCNT write takes precedence and the TCFV flag in TSR is not set.
Figure 10.54 shows the operation timing when there is contention between TCNT write and
overflow.
10.10.13 Multiplexing of I/O Pins
In the H8S/2268 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the
TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and
the TCLKD input pin with the TIOCB2 I/O pin. In the H8S/2264 Group, the TCLKC input pin is
multiplexed with the TIOCB1 I/O pin. When an external clock is input, compare match output
should not be performed from a multiplexed pin.
10.10.14 Interrupts in Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source, or the DTC activation source (the H8S/2268 Group only).
Interrupts should therefore be disabled before entering module stop mode.
Rev. 5.00 Sep. 01, 2009 Page 256 of 656
REJ09B0071-0500
Figure 10.54 Contention between TCNT Write and Overflow
Address
Write signal
TCNT
TCFV flag
φ
H'FFFF
Prohibited
TCNT write cycle
TCNT address
T1
T2
M
TCNT write data