DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 12

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
5.6.5 IRQ Interrupt
5.6.6 NMI Interrupt
Usage Notes
6.3.4 Operation in
Transitions to Power-
Down Modes
8.2.5 DTC Transfer
Count Register A
(CRA)
8.5 Operation
Figure 8.5 Flowchart
of DTC Operation
9.1.1 Port 1 Data
Direction Register
(P1DDR)
Rev. 5.00 Sep. 01, 2009 Page x of l
REJ09B0071-0500
Page
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102
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Revision (See Manual for Details)
5.6.5 added
5.6.6 added
Description deleted
• When the SLEEP instruction causes a transition from high
Description amended
In repeat mode or block transfer mode, the CRA is divided into
two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL).
In repeat mode, CRAH holds the number of transfers while
CRAL functions as an 8-bit transfer counter (1 to 256). In block
transfer mode, CRAH holds the block size while CRAL functions
as an 8-bit block size counter (1 to 256). CRAL is decremented
by 1 every time data is transferred, and the contents of CRAH
are sent when the count reaches H'00. This operation is
repeated.
Figure amended
Description added
P1DDR specifies input or output of the port 1 pins using the
individual bits. P1DDR cannot be read; if it is, an undefined
value will be read.
The value of this register when read is undefined after a bit
manipulation instruction is executed. To prevent undefined read
values, do not use bit manipulation instructions to write to this
register. For details, see section 2.9.4, Access Methods for
Registers with Write-Only Bits.
speed
Note: * For details, see section related to each peripheral module.
Clear an activeation flag
Transfer Counter = 0
or DISEL = 1
No
mode to subactive mode (figure 6.2 (B)).
End
Yes
Interupt exception
Clear DTCER
handling
*