DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 369

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Legend:
X: Don’t care
Bit
3
2
1
0
Bit Name
MPIE
TEIE
CKE1
CKE0
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
Description
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in Smart Card interface mode.
When receive data including MPB = 0 is received, receive
data transfer from RSR to RDR, receive error detection,
and setting of the RERF, FER, and ORER flags in SSR,
are not performed.
When receive data including MPB = 1 is received, the
MPB bit in SSR is set to 1, the MPIE bit is cleared to 0
automatically, and generation of RXI and ERI interrupts
(when the TIE and RIE bits in SCR are set to 1) and FER
and ORER flag setting are enabled.
Transmit End Interrupt Enable
Write 0 to this bit in Smart Card interface mode.
TEI cancellation can be performed by reading 1 from the
TDRE flag in SSR, then clearing it to 0 and clearing the
TEND flag to 0, or clearing the TEIE bit to 0.
Clock Enable 0 and 1
Enables or disables clock output from the SCK pin. The
clock output can be dynamically switched in GSM mode.
For details, refer to section 13.7.8, Clock Output Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin can be used as an I/O port
01: Clock output
1X: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
pin)
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Sep. 01, 2009 Page 317 of 656
REJ09B0071-0500