DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 399

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Figure 13.12 Sample Serial Reception Data Flowchart (1)
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Read ORER, PER, and
PER∨FER∨ORER = 1
All data received?
FER flags in SSR
Start reception
Initialization
RDRF = 1
<End>
Yes
Yes
No
(Continued on next page)
Error processing
Yes
[1]
[2]
[4]
[5]
[3]
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Sep. 01, 2009 Page 347 of 656
[1] SCI initialization:
[2] [3] Receive error processing and break
[4] SCI status check and receive data read:
[5] Serial reception continuation procedure:
Note: * The case, in which the DTC
The RxD pin is automatically
designated as the receive data input
pin.
detection:
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
appropriate error processing, ensure
that the ORER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
The RDRF flag is cleared automatically
when DTC * is activated by an RXI
interrupt and the RDR value is read.
(H8S/2268 Group only)
automatically clears the RDRF flag,
occurs only when DISEL in DTC is
0 with the transfer counter not
being 0. Therefore, the RDRF flag
should be cleared by CPU when
DISEL is 1, or when DISEL is 0
with the transfer counter being 0.
REJ09B0071-0500