DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 281

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• PWM mode 2
The correspondence between PWM output pins and registers is shown in table 10.18.
Table 10.18 PWM Output Registers and Output Pins
Notes: 1. Supported only by the H8S/2268 Group.
Channel
0 *
1
2
1
H8S/2264 Group:
PWM output is generated from the TIOCA pin by pairing TGRA with TGRB. The output
specified by bits IOA0 to IOA3 in TIOR is output from the TIOCA pin at compare match A,
and the output specified by bits IOB0 to IOB3 in TIOR is output at compare match B. The
initial output value is the value set in TGRA. If the set values of paired TGRs are identical, the
output value does not change when a compare match occurs.
In PWM mode 1, PWM output is enable up to 2 phases.
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, PWM output is enabled up to 7 phases in the H8S/2268 Group or 3 phases in
the H8S/2264 Group by using also synchronous operation.
2. In PWM mode 2, PWM output is not possible for the TGR register in which the period is
set.
Registers
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
PWM Mode 1
TIOCA0
TIOCC0
TIOCA1
TIOCA2
Rev. 5.00 Sep. 01, 2009 Page 229 of 656
Section 10 16-Bit Timer Pulse Unit (TPU)
Output Pins
PWM Mode 2 *
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
REJ09B0071-0500
2