DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 40

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 5.6
Figure 5.7
Figure 5.8
Figure 5.9
Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 ............... 95
Figure 5.11 Interrupt Exception Handling ................................................................................. 96
Figure 5.12 DTC and Interrupt Controller................................................................................. 99
Figure 5.13 Contention between Interrupt Generation and Disabling ....................................... 101
Section 6 PC Break Controller (PBC)
Figure 6.1
Figure 6.2
Section 7 Bus Controller
Figure 7.1
Figure 7.2
Figure 7.3
Section 8 Data Transfer Controller (DTC)
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) .................. 132
Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, with Block
Figure 8.12 DTC Operation Timing (Example of Chain Transfer) ........................................... 133
Section 9 I/O Ports
Figure 9.1
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU for H8S/2268 Group......................................................... 188
Figure 10.2 Block Diagram of TPU for H8S/2264 Group......................................................... 189
Figure 10.3 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ..................... 216
Rev. 5.00 Sep. 01, 2009 Page xxxviii of l
REJ09B0071-0500
IWPFn Setting Timing ........................................................................................... 83
Block Diagram of Interrupt Control Operation for H8S/2268 Group .................... 89
Block Diagram of Interrupt Control Operation for H8S/2264 Group .................... 90
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control
Mode 0 ................................................................................................................... 93
Block Diagram of PC Break Controller ................................................................. 104
Operation in Power-Down Mode Transitions ........................................................ 108
On-Chip Memory Access Cycle............................................................................. 111
On-Chip Peripheral Module Access Cycle (H'FFFDAC to H'FFFFBF) ................ 112
On-Chip Peripheral Module Access Cycle (H'FFFC30 to H'FFFCA3) ................. 113
Block Diagram of DTC .......................................................................................... 116
Block Diagram of DTC Activation Source Control ............................................... 123
The Location of DTC Register Information in Address Space .............................. 124
Correspondence between DTC Vector Address and Register Information ............ 124
Flowchart of DTC Operation ................................................................................. 127
Memory Mapping in Normal Mode ....................................................................... 128
Memory Mapping in Repeat Mode ........................................................................ 129
Memory Mapping in Block Transfer Mode ........................................................... 130
Chain Transfer Operation....................................................................................... 131
Size of 2) ................................................................................................................ 133
Types of Open Drain Outputs ................................................................................ 154