DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 478

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
14.4.8
The I
the slave address and the R/W bit, confirmation of reception with acknowledge bit, indication of
the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in
conjunction CPU processing by means of interrupts.
Table 14.5 shows some example of processing using the DTC. These examples assume that the
number of transfer data bytes is know in slave mode.
Table 14.5 Flags and Transfer States
Rev. 5.00 Sep. 01, 2009 Page 426 of 656
REJ09B0071-0500
Item
Slave address +
R/W bit
Transmission/
reception
Dummy data
read
Actual data
transmission/re
ception
Dummy data
(H′FF) write
Last frame
processing
Transfer
request
processing after
last frame
processing
Setting of
number of DTC
transfer data
frames
2
C bus format provides for selection of the slave device and transfer direction by means of
Operation Using the DTC (H8S/2268 Group Only)
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Master Transmit
Mode
Transmission by
DTC (ICDR write)
⎯
Transmission by
DTC (ICDR write)
⎯
Not necessary
1st time: Clearing
by CPU
2nd time: End
condition issuance
by CPU
Transmission:
Actual data count
+ 1 (+ 1
equivalent to
slave address +
R/W bits)
Master Receive
Mode
Transmission by
CPU (ICDR write)
Processing by
CPU (ICDR read)
Reception by DTC
(ICDR read)
⎯
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count
Slave Transmit
Mode
Reception by CPU
(ICDR read)
⎯
Transmission by
DTC (ICDR write)
Processing by DTC
(ICDR write)
Not necessary
Automatic clearing
on detection of end
condition during
transmission of
dummy data (H′FF)
Transmission:
Actual data count +
1 (+ 1 equivalent to
dummy data (H′FF))
Slave Receive
Mode
Reception by CPU
(ICDR read)
⎯
Reception by DTC
(ICDR read)
⎯
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count