DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 467

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the
[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,
[3] The IRIC flag is set to 1 by the following two conditions. At that point, an interrupt request
[4] Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by
[5] If the IRTR flag value is 1, read the ICDR receive data.
[6] Clear the IRIC flag to 0. The reading of the ICDR flag described in step [5] and the clearing
[7] Set the ACKB bit in ICSR to 1 to set the acknowledge data for the final receive.
[8] Wait for at least 1 clock cycle after the IRIC flag is set to 1 and then wait for the rising edge
[9] Set the TSR bit in ICCR to 1 to switch from the receive mode to the transmit mode. The TSR
[10] Read the ICDR receive data.
[11] Clear the IRIC flag to 0. As in step [6], read the ICDR flag and clear the IRIC flag to 0
Further data can be received by repeating steps [3] through [6].
ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0, then set the
WAIT bit in ICMR to 1.
and data received, in synchronization with the internal clock.
is issued to the CPU if the IEIC bit in ICCR is set to 1.
(1) The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame.
(2) The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame.
clearing the IRIC flag as described in step [6] below. If the IRTR flag value is 1 and the next
receive data is the final receive data, perform the end processing described in step [7] below.
of the IRIC flag to 0 should be performed consecutively, with no interrupt processing
occurring between them. During wait operation, clear the IRIC flag to 0 when the value of
counter BC2 to BC0 is 2 or greater. If the IRIC flag is cleared to 0 when the value of counter
BC2 to BC0 is 1 or 0, it will not be possible to determine when the transfer has completed. If
condition [3]-1 is true, the master device drives SDA to low level and returns an
acknowledge signal when the receive clock outputs the 9th clock cycle.
of the 1st clock cycle of the next receive data.
bit setting value at this point becomes valid when the rising edge of the next 9th clock cycle
is input.
consecutively, with no interrupt processing occurring between them. During wait operation,
clear the IRIC flag to 0 when the value of counter BC2 to BC0 is 2 or greater.
SCL is automatically held low, in synchronization with the internal clock, until the IRIC
flag is cleared.
The IRTR flag is set to 1, indicating that reception of 1 frame of data has ended. The
master device continues to output the receive clock for the receive data.
Section 14 I
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Rev. 5.00 Sep. 01, 2009 Page 415 of 656
REJ09B0071-0500