DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 410

IC H8S/2268 MCU FLASH 100QFP

DF2268FA13V

Manufacturer Part Number
DF2268FA13V
Description
IC H8S/2268 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2268FA13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2268FA13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Sep. 01, 2009 Page 358 of 656
REJ09B0071-0500
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Start transmission
Figure 13.20 Sample Serial Transmission Flowchart
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
No
No
No
[3]
[2]
[1]
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
Note: * The case, in which the DTC
The TxD pin is automatically
designated as the transmit data output
pin.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC * is
activated by a transmit data empty
interrupt (TXI) request and data is
written to TDR. (H8S/2268 Group
only)
automatically clears the TDRE
flag, occurs only when DISEL in
DTC is 0 with the transfer counter
not being 0. Therefore, the TDRE
flag should be cleared by CPU
when DISEL is 1, or when DISEL
is 0 with the transfer counter
being 0.

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